This invention relates generally to data storage systems, and more particularly to data storage systems wherein a variable stored in the system may be processed by a plurality of system resources.
As is known in the art, large mainframe or open system (i.e., host) computer systems require large capacity data storage systems. These host computer systems generally includes data processors which perform many operations (i.e., functions) on data introduced to the computer system through peripherals including the data storage system. The results of these operations are output to peripherals, including the storage system.
One type of data storage system is a magnetic disk storage system. Here a bank of disk drives and the host computer system are coupled together through an interface. The interface includes CPU, or "front end", controllers and "back end" disk controllers. The interface operates the controllers in such a way that they are transparent to the computer. That is, data is stored in, and retrieved from, the bank of disk drives in such a way that the host computer system merely thinks it is operating with one host computer memory. One such system is described in U.S. Pat. No. 5,206,939, entitled "System and Method for Disk Mapping and Data Retrieval", inventors Moshe Yanai, Natan Vishlitzky, Bruno Alterescu and Daniel Castel, issued Apr. 27, 1993, and assigned to the same assignee as the present invention.
As described in such U.S. Patent, the interface may also include, in addition to the CPU controllers and disk controllers, addressable cache memories. The cache memory is a semiconductor memory and is provided to rapidly store data from the host computer system before storage in the disk drives, and, on the other hand, store data from the disk drives prior to being sent to the host computer. The cache memory being a semiconductor memory, as distinguished from a magnetic memory as in the case of the disk drives, is much faster than the disk drives in reading and writing data.
The CPU controllers, disk controllers and cache memory are interconnected through a backplane printed circuit board. More particularly, disk controllers are mounted on disk controller printed circuit boards. CPU controllers are mounted on CPU controller printed circuit boards. And, cache memories are mounted on cache memory printed circuit boards. The disk controller, CPU controller and cache memory printed circuit boards plug into the backplane printed circuit board. In order to provide data integrity in case of a failure in a controller, the backplane printed circuit board has a pair of busses. One set the disk controllers is connected to one bus and another set of the disk controllers is connected to the other bus. Likewise, one set the CPU controllers is connected to one bus and another set of the CPU controllers is connected to the other bus. The cache memories are connected to both busses. Thus, the use of two busses provides a degree of redundancy to protect against a total system failure in the event that the controllers, or disk drives connected to one bus fail.
In one system, the communication to the controllers and the cache memories is through a pair of bi-directional lines. Typically one bi-directional line is for data and the other bi-directional line is for control signals. As noted above, each of the controllers is connected to only one of the busses and, therefore, only one pair of bi-directional lines are electrically connected to the controllers; however, because each one of the cache memories is connected to both busses, each cache memory has two pairs of bi-directional lines.
During the operation of such a system, functional operations may be required to be performed by various system resources on a global variable stored in the system. If one resource has acquired the variable for one type of functional operation, it is important that the variable not be operated upon by another requesting system resource until the first resource has performed its operation on the variable. Thus, in many systems the variable is locked (i.e, made non-accessible by any of the other resources) until the variable has been operated on by the first resource. The locking of the variable, however, requires loss of full utilization of all system resources. For example, in the system described above, a controller requesting transfer of an addressed variable must poll the system to determined whether the variable is being operated upon by another one of the resources. This polling takes places during steps in the desired operation on the variable to see whether the variable is released from any locked condition. During the polling, the system busses are tied up thereby reducing the efficiency of the system.